Field programmable gate arrays (FPGAs) are composed of a finite number of predefined resources with programmable interconnects. These programmable interconnects implement user-defined logic circuitry on the FPGA. Logic circuit designers write code in a hardware description language (HDL) which describes how logic blocks are wired together on the FPGA to implement a desired circuit. The code is passed through proprietary compilation tools that translate the desired circuit into FPGA configuration bits. These FPGA configuration bits are primarily in the form of look-up table (LUT) contents and switch matrix configurations which are customized for the desired circuit.
The process of compiling HDL code into FPGA configuration bits, known as synthesis/place-and-route (PAR), can require up to several hours and even days for completion, depending on the size and complexity of the circuit to be implemented. In order to apply updates to an FPGA-mapped circuit (e.g., implemented data processing functions), the circuit designer first updates the HDL code, then configuration bits are re-generated, and finally the FPGA is re-programmed. Although certain FPGA vendors provide support for reconfiguring user-defined regions of the FPGA, this partial reconfiguration process is cumbersome, resource wasteful, and synthesis (i.e., compilation) is still required, albeit for a smaller subset of the FPGA. Partial reconfiguration also imposes restrictions on the placement of user functions, and is thus undesirable.